Fault Tolerant Finite State Control using Low Density Parity Checking

Digital technology in space-bound, nanometer scale systems create the need for reliable computation in the face of a small but finite error rate. We present a designerdriven, semi-automated technique for synthesizing fault tolerance in finite state machines. This is done with lower implementation overhead in terms of both machine redundancy and overall logic complexity than conventional methods. We further show that it is possible to generate efficient encodings that inherently provide tolerance to constant error rates in excess of one error per cycle and, through the use of a high level description language (HDL), can be performed with turn-key simplicity. The technique is demonstrated in the design of a practical multi-threaded microprocessor engineered specifically for real-time and high bandwidth control. Comparison between the basic and fault tolerant versions shows that as large as 18% error rates can be recovered with minimal space overhead and almost no